1. Machine B runs at 2 GHz and has a CPl of 1.3 for a particular program. Machine C runs at5 GHz and has a CPI of 2.4 for that program, while executing 20% more instructions. Which machine is faster? What is the speedup over the slower machine? 2. (Amdahl's law backwards) You have an optimization that speeds up only the non- memory operations by a factor of 3, If you spend 50% of your execution time waiting for memory after the optimization, what percentage of the original execution time did you wait for memory? 3. Suppose you change the MIPS ISA from a 3-address to a 2-address ISA (destination register is the same as the second ALU operand), and you double the number of registers, how many new R-type instructions can you support? How many fewer I-type instructions can you support, assuming you still want to use 16-bit immediates