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Princess Sumaya University for Technology

Computer Engineering Department

Digital Logic Lab

Final Project $-$ Fall $2023$

Princess Sumaya d$\_$act

for Technology Unersity

Due Date: $\frac{14}{1}\frac{?}{2024}$

Project Description:

Implement the transmitter$/$receiver circuit shown in Figure $1$ using Verilog. The circuit can be implemented using any type of model $($Behavioral$,$ structural $...$etc$)$ and should meet the following requirements:

Figure $1.$ Circuit Diagram

The circuit's functionality: In this circuit, the transmitter reads data from the source memory and sends it to the receiver, which is responsible for storing the data in the receiving memory.

Design Requirements:

The starting address of where to read the data is stored in Source Reg.

The starting address of where to store the data is stored in Dest. Reg.

The copy should stop when it reaches this special data pattern $=FFF{F}_h.$ It should copy it$,$ then stop.

The transmitter operates on the negative edge, while the receiver operates at the positive edge.

The transmitter prepares an EVEN parity bit and sends it with the data.

The Err? Block receives one bit and outputs one bit immediately $($i$.$e$.$ it does not wait for the clock$).$ The block sometimes flips the input bit to introduce error in the data transmission, while other times it does not. Students can pick whatever method to implement this. The clock connected to the block is just to change the state of the block.

If the transmitter reaches the last address $(4095),$ it should stop.

The receiver should include a parity checker inside it$.$

If the receiver reaches the last address, it should raise the Full flag, and consequently, the transmitter would stop.

The circuit should follow the following transmission sequence: