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1 ) On startup we look at detecting the sequence 0 0 0 first and then 0 0 0 again ( no overlap allowed )

1) On startup we look at detecting the sequence 000 first and then 000 again (no overlap allowed).
2) After the leading sequence (000) is detected twice (not necessarily consecutively), without overlap, we ignore subsequent instances of 000s and look to detect the sequence 111 once.
3) After a sequence 111 is detected once, we ignore subsequent instances of 111s and look again to detect the sequence 000 twice. The process continues alternating between the detection of the 000 sequence twice and then the 111 sequence once.
4) The timing trace shown below depicts a possible example, using Moore, depicting some detections events in order to clarify the prescribed functionality for this FSM.
5) If possible, provide alternative design solutions stating any trade-offs among them.
6) Use LogiSim to verify, and demonstrate to the instructor, that your design works as intended.
Design Constraints:
(Note: Every time you cannot meet one of the constraints you may lose a few points.)
1. Try not to use more than 4 Flip-Flops of any type.
2. Try to minimize the discrete gate count. State what you did in order to minimize the gate count.
3. The system can be a single FSM or use any number of subsystems (for example one subsystem for each sequence to be detected).
4. You may use more Flip Flops, if needed, when providing alternative design solutions. In such case discuss pros and cons.
5. Recall that no overlap is allowed when detecting 000 twice.
6. You can use Moore or Mealy FSMs.
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