1. Operand Reduction

Consider the design of an instruction set for a machine with:

a one-byte opcode;

a word-size of 32 bits;

a byte-addressable memory of size 2208;

a register file of size 832.

Note that the word-size does not equal the smallest addressable grain-size of memory: it is a multiple.That is typical for most machines. It is possible, therefore, that several instructions (up to 4) could occupy a single word of memory. An efficiently designed CPU would typically fetch that word only once and retain the result internally, rather than waste time on 4 separate fetches. This will be factored into our calculations by counting the number of bytes accessed on fetch, decode and execute, rather than the number of words.

(a) Consider the design of a 3-operand machine. The desired addressing modes include immediate mode, direct mode and relative mode.

movi $val, rC rC$val

movmr addr, rC rCM[addr]

movrr rA, rC rCrA

movrm rA, addr M[addr]rA

add rA, rB, rC rCrA+rB

jle rA, rB, disp ifrArB,PC+=disp

Design a set of instruction formats for these 6 instructions. Your design should allow each explicit operand to encode its full range of values.Present your answer in table format, one instruction per row. The two rightmost columns should contain a measure of how many bytes would be loaded on fetch+decode, and how many would be read/written on execute.

(b)Create alternate versions of movi and jle that offer a restricted range of values, but a shorter instruction length:

movi $val21, rC rC$val21 21-bit signed $val

jle rA, rB, disp10 if rArB , PC+=disp10 10-bit signed disp

Add two more rows to your table to include these versions. State the range of each operand

(c) [2 marks] Redevelop the instruction formats for a 2-operand machine. The only instructions that need to change would be add and jle.

add rA, rC rCrC+rA

jle rA, disp if rA0,PC+=disp

jle rA, disp5 if rA0,PC+=disp5 5-bit signed disp

Add these to your table.

Note:To achieve full marks, your instruction formats should be as consistent as possible with those developed in parts (a) and (b). You may need to re-tune your answer to (a) and (b) to arrive at the best overall result.

(d) Write a program that, for a trio of 32-bit values x,y,z, computes z(x+y)(xy). You may also use sub and mul, which will have the same instruction format as add.Write two versions: one for the 3-operand machine and one for the 2-operand machine. Total the number of bytes of memory access that are done during each of fetch+decode, and execute, and conclude which system is better.

(e) Using your ISA from (a), (b), (c), write a version of the program that consumes no more than 30 bytes of memory