1) Perform simple behavioral optimization: optimize the computation by simplifying the algebraic expression for ul to minimize the total area cost of all arithmetic operations involved. Use the table given below to calcu- late the cost. Make sure that you consider all possible means of optimiza- tion, such as (wherever applicable) factorization, constant propagation, replacement of constant multiplication by shift & add, etc. This should reduce the area cost of the design, without negatively affecting the latency. 2) Minimize the latency of the design, measured in the number of clock cycles, using delay data shown in the table. 3) For the computed minimum latency L, find the schedule which mini- mizes the total area cost of the design (not just the number of operators). . 4) Minimize the number of registers needed to store intermediate results. For simplicity assume that the primary inputs (x, y, u, dx, and constant 3) do not need registers. . 5) Draw a detailed block-level diagram (architecture) of the design and clearly show the data path elements, steering logic (MUXes, wiring, etc.), registers, and the interface with the control logic. Try to place registers close to the outputs of the operators (some steering logic may still be required). (Check examples of final architecture shown in lecture 1 slides, lec-1.pdf slide 19). Perform a simple mental simulation to make sure that your architecture indeed implements the computation specified by this DFG and that the intermediate data is correctly stored in the registers. The following table shows the available resources (library of arithmetic op- rators) and their area and delay cost. Your design will use clock cycle of 10 ns. u dx 3 dr 10 dx y x1 yl 5 Figure 1: Data Flow Graph (DFG) of the design. Unit type Operations Area (um2) ALU add(+), sub(-), comp 40 Shift shift (1) 20 MULT mult (2 100 Delay (ns) 8 6 28 1) Perform simple behavioral optimization: optimize the computation by simplifying the algebraic expression for ul to minimize the total area cost of all arithmetic operations involved. Use the table given below to calcu- late the cost. Make sure that you consider all possible means of optimiza- tion, such as (wherever applicable) factorization, constant propagation, replacement of constant multiplication by shift & add, etc. This should reduce the area cost of the design, without negatively affecting the latency. 2) Minimize the latency of the design, measured in the number of clock cycles, using delay data shown in the table. 3) For the computed minimum latency L, find the schedule which mini- mizes the total area cost of the design (not just the number of operators). . 4) Minimize the number of registers needed to store intermediate results. For simplicity assume that the primary inputs (x, y, u, dx, and constant 3) do not need registers. . 5) Draw a detailed block-level diagram (architecture) of the design and clearly show the data path elements, steering logic (MUXes, wiring, etc.), registers, and the interface with the control logic. Try to place registers close to the outputs of the operators (some steering logic may still be required). (Check examples of final architecture shown in lecture 1 slides, lec-1.pdf slide 19). Perform a simple mental simulation to make sure that your architecture indeed implements the computation specified by this DFG and that the intermediate data is correctly stored in the registers. The following table shows the available resources (library of arithmetic op- rators) and their area and delay cost. Your design will use clock cycle of 10 ns. u dx 3 dr 10 dx y x1 yl 5 Figure 1: Data Flow Graph (DFG) of the design. Unit type Operations Area (um2) ALU add(+), sub(-), comp 40 Shift shift (1) 20 MULT mult (2 100 Delay (ns) 8 6 28
