1 Pipeline: A (fictional) CPU has the following functional units and timings 1. ID - 200 ps (instruction decode) 2. RR 100 ps (read registers) 3. WR 110 ps (write registers) 4. ALU - 180 ps (integer and logic) 5. FPU - 280 ps (loating point) 6. MEM - 200 ps (memory read/write) There are 5 basic instruction types: 1. LOAD ID+RR+ALU+MEM+WR : 790ps 2. STORE: ID+RR+ALU+MEM: 680ps 3. LOGIC/INTEGER: ID+RR+ALU+WR: 590ps 4. FLOATING POINT: ID+RR+FPU+WR: 690ps 5. BRANCH: ID+RR+ALU: 480ps 1 cycle is 790ps for the unpipelined machine, on the assumption that all instruc- tions take 1 cycle (ignore memory delays). Design a pipeline for this machine. Specify A) How many stages, B) What functional units are in each stage, C) What is the new clock rate, D) What is the speedup over the original machine