1. please add an int variable to my VHDLcode where I can incorporate and stored value function

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library ieee;

use ieee.std_logic_1164.all;

-- Entity declaration

entity register_8bit is

Port (

-- Clock input

clk : in std_logic;

-- Data input

din : in std_logic_vector (7 downto 0);

-- Data output

dout : out std_logic_vector (7 downto 0)

);

end register_8bit;

-- Architecture declaration

architecture behavioral of register_8bit is

-- Signal to store the value of the input

signal stored_value : std_logic_vector (7 downto 0);

begin

-- Process to update the stored value on every rising edge of the clock

process (clk)

begin

if (clk'event and clk = '1') then

-- Update the stored value with the current input

stored_value <= din;

end if;

end process;

-- Assign the stored value to the output

dout <= stored_value;

end behavioral;

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2. please help me create a test bench for my code .

I WILL LIKE ASAP PLS