1. Please show only structural hazards. mov [100], [150] mov [200], [250] add [150], [250], r3 sub r3, #5, r4 add r3, #2, r5 div r4, r5, r6 Instruction encoding: instruction op1, op2, result; [xxxx] memory address; #x constant; rx register. 2. Please show only data hazards. mov [100], [150] mov [200], [300] add [100], [150], [300] add [300], #100, [322] add [300], #200, [333] sub [250], [333], [326]

4. Write program (in pseudo assembler code) for register-register (load/store) architecture CPU witch does C=A-B+A*B and optimize this program in pipeline (to avoid hazard stalls).