1 S/1/S15/25/10/15] KA.2> Use the following code fragment: Loop:LD R1,0(R2) load R1 from address 0+R2 R1,R1,#1 R1,0, (R2) store R1 at address 0+R2 R2,R2,4 R4,R3,R2 DADDI DADDI DSUB BNEZ :branch to Loop if R4!-0 Assume that the initial value of R3 is R2+396. a. [151 Data hazards are caused by data dependences in the code. Whether a dependency causes a hazard depends on the machine implementa tion (i.e., number of pipeline stages). List all of the data dependences in the code above. Record the register, source instruction, and destination instruc- tion; for example, there is a data dependency for register R1 from the LD to the DADDI b. [15] Show the timing of this instruction sequence for the S-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the reg- ister file, as shown in Figure C.6. Use a pipeline timing chart like that in Fig ure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cyeles does this loop take to exe- [151 Show the timing of this instruction sequence for the 5-stage RIS pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled by predicting it as not taken. If all memory references take I cycle, how many cycles does this loop take to execute? c. d. [15l Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled by predicting it as taken. If all memory references take I cycle, how many cycles does this loop take to execute? 1 S/1/S15/25/10/15] KA.2> Use the following code fragment: Loop:LD R1,0(R2) load R1 from address 0+R2 R1,R1,#1 R1,0, (R2) store R1 at address 0+R2 R2,R2,4 R4,R3,R2 DADDI DADDI DSUB BNEZ :branch to Loop if R4!-0 Assume that the initial value of R3 is R2+396. a. [151 Data hazards are caused by data dependences in the code. Whether a dependency causes a hazard depends on the machine implementa tion (i.e., number of pipeline stages). List all of the data dependences in the code above. Record the register, source instruction, and destination instruc- tion; for example, there is a data dependency for register R1 from the LD to the DADDI b. [15] Show the timing of this instruction sequence for the S-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the reg- ister file, as shown in Figure C.6. Use a pipeline timing chart like that in Fig ure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cyeles does this loop take to exe- [151 Show the timing of this instruction sequence for the 5-stage RIS pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled by predicting it as not taken. If all memory references take I cycle, how many cycles does this loop take to execute? c. d. [15l Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled by predicting it as taken. If all memory references take I cycle, how many cycles does this loop take to execute