1. Several researchers have suggested that adding a register-memory addressing mode to a load-store computer might be useful. The idea is to replace sequences of LOAD R1,0(R) ADD R2,R2,R1 by ADD R2,0(Rb) Assume the new instruction will cause the clock cycle to increase by 5%. Use the instruction frequencies for the gee benchmark on the load-store computer from Figure 2.32. The new instruction affects only the clock cycle and not the CPI. 1. Several researchers have suggested that adding a register-memory addressing mode to a load-store computer might be useful. The idea is to replace sequences of LOAD R1,0(R) ADD R2,R2,R1 by ADD R2,0(Rb) Assume the new instruction will cause the clock cycle to increase by 5%. Use the instruction frequencies for the gee benchmark on the load-store computer from Figure 2.32. The new instruction affects only the clock cycle and not the CPI