1. Suppose you have a cached computer system with 1M words in main memory and a cache size of 4K words. Assume main memory is divided into blocks with each block containing 16 words. Assume word addressing.

(a) If the cache uses direct mapping, what cache frame does the physical (hex) address 0x949DA map into? What value needs to be in that cache frames tag to get a cache hit?

(b) Assume a set associative cache with 64 sets of 4 block frames per set. What set does the physical (hex) address 0x949DA map into? How many bits are there in each cache tag? What is the cache tag (in hex) for this physical address?

(c) If the cache is fully associative, what is the cache tag for the physical (hex) address 0x949DA?

2. Suppose you have a cached computer system with a main memory size of 32K words and a cache size of 4K words. The cache is fully associative with a block size of 8 words.

Assume word addressing.

(a) How many hardware comparators are needed to support the fully associative cache?

(b) What is the size of the tag field?

(c) How many hardware comparators would be needed to support a direct mapped cache? What would be the size of the tag field with a direct mapped cache?