1) The Cortex M0+ processor supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An interrupt or exception changes the normal how of software control. Explain the sequence of steps that occurs during interrupt processing. How many interrupts latency from exception request to execution of the first instruction in the interrupt handler? 

2) An ISR refers to the Interrupt Service Routines. These are procedures stored at specific memory addresses which are called when a certain type of interrupt occurs. The Cortex M0+ processors family has the Nested Vectored Interrupt Controller (NVIC) that manages the execution of the interrupt. Propose what are the things that need to pay attention to when users design an ISR.