1. The following figure is a Parallel-In-Serial-Out (PISO) shift register. Each flip- flop used in the shift register is a rising edge triggered D flip-flop. Serial 2 CLK (1) How many clock pulses do you need to shift a 4-bits data into the register if the SHIFT/LOAD' control signal is high? (2) How many clock pulses do you need to load a 4-bits data into the register the SHIFT/LOAD' control signal is low? )Assume the the SHIFT/LOAD' control signal is high, the original output values Q0 Q1 Q2 Q3 are "0101" before the first clock edge. The input p DO is connected with a constant high ("1"). What are the values of Q0 Q1 Q2 Q3 after the third clock edge? 1. The following figure is a Parallel-In-Serial-Out (PISO) shift register. Each flip- flop used in the shift register is a rising edge triggered D flip-flop. Serial 2 CLK (1) How many clock pulses do you need to shift a 4-bits data into the register if the SHIFT/LOAD' control signal is high? (2) How many clock pulses do you need to load a 4-bits data into the register the SHIFT/LOAD' control signal is low? )Assume the the SHIFT/LOAD' control signal is high, the original output values Q0 Q1 Q2 Q3 are "0101" before the first clock edge. The input p DO is connected with a constant high ("1"). What are the values of Q0 Q1 Q2 Q3 after the third clock edge