1) The timing cycle for the Load Accumulator (LDA) instruction, using direct access to memory M is provided below. The notation used is the same as in the lecture notes. Note that the register transfer level (RTL) micro-operations listed are also consistent with the lecture notation (and attributed to M. Mano).

T0 : AR = PC, SC = SC + 1

T1 : DR = M[AR], IR = M[AR], PC = PC + 1, SC = SC + 1

T2 : {D7,D6,...,D1,D0} = DEC( IR(12-14) ), I = IR(15), AR = IR(0-11), SC = SC + 1 I' D2

T3 : AC = M[AR], SC = 0

The registers PC, AR, IR, SC and AC are the same as defined in the lecture notes, while the I and DECoder outputs Dx and timing decoder outputs Tx are also the same as defined in the lecture notes. Draw a complete and well-labeled block diagram for this circuit, showing how the various connections must be made to control the timing sequence for the LDA instruction cycle. Hint: Note that the entire circuit, and each individual element within the circuit (such as individual registers) are always ready to perform their function and are just waiting for an enable condition to be fulfilled so they can proceed. Thus, it is useful to isolate the various components of the LDA circuit and determine what conditions must be fulfilled in order to direct enabling of sub-circuit elements.

2) The timing cycle for the Load Accumulator (LDA) instruction, using indirect access to memory M is provided below. The notation used is the same as in the lecture notes. Note that the register transfer language and microoperations listed are also consistent with Mano's notation. T0 : AR = PC, SC = SC + 1 T1 : DR = M[AR], IR = M[AR], PC = PC + 1, SC = SC + 1 T2 : {D7,D6,...,D1,D0} = DEC( IR(12-14) ), I = IR(15), AR = IR(0-11), SC = SC + 1 I D2 T3 : DR = M[AR], SC = SC + 1 I D2 T4 : AR = DR(0-11), SC = SC + 1 I D2 T5 : AC = M[AR], SC = 0 The registers PC, AR, IR, DR, SC and AC are the same as defined by Mano (and lecture notes), while the I and DECoder outputs Dx and timing decoder outputs Tx are also the same as defined by Mano. Based on the block diagram for Question 1 above, draw a block diagram for the different aspects of this circuit that perform the extra memory fetch and indicate whether there should be any changes to the direct addressing LDA. Also, show how the various connections must be made between your answer to this question and the diagram of Question 1 to control the timing cycle of the indirect addressing mode of the LDA instruction.