1) Use the following code fragment 4.R4. #4 O(R4) R6, R6 8, 0(R1) 1,R1, #4 R4, R2 Loop DADDI LW DADDI SUB BNEZ Assume that the initial value of R2 is R4 + 192 Assume early evaluation of branch instruction, i.e., the branch outcome (whether the condition is true or false and where is the next instruction) is known after the Decode stage., but the branch instruction will still go through all the five pipeline stages . For both la and 1b, assume that the branch is handled by predicting it as not taken, i.e. the next instruction in program sequence is fetched (Continue with next instruction as usual). However, it is a wrong instruction except for the last iteration, and wil1 be flushed after the branch outcome is known. 1a. Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the register file, as shown in Figure C.6. Use a pipeline timing chart like that in Figure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to execute? 1b. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. If all memory references take 1 cycle, how many cycles does this loop take to execute? 1) Use the following code fragment 4.R4. #4 O(R4) R6, R6 8, 0(R1) 1,R1, #4 R4, R2 Loop DADDI LW DADDI SUB BNEZ Assume that the initial value of R2 is R4 + 192 Assume early evaluation of branch instruction, i.e., the branch outcome (whether the condition is true or false and where is the next instruction) is known after the Decode stage., but the branch instruction will still go through all the five pipeline stages . For both la and 1b, assume that the branch is handled by predicting it as not taken, i.e. the next instruction in program sequence is fetched (Continue with next instruction as usual). However, it is a wrong instruction except for the last iteration, and wil1 be flushed after the branch outcome is known. 1a. Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the register file, as shown in Figure C.6. Use a pipeline timing chart like that in Figure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to execute? 1b. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. If all memory references take 1 cycle, how many cycles does this loop take to execute