1. Using the 2-way set associative D-cache depicted below; give the result of the following memory accesses. These memory accesses are byte fetches.

a. The result should be in the format of H: (hit), CM: (compulsory miss) or M: (miss).

b. Use the LRU replacement policy; assuming that 0 denotes LRU and 1 denotes MRU.

c. If you replace a block, assume that only the tag is changed and the data (marked as X) is unchanged.

d. All numeric values are in hexadecimal.

2. Consider a direct mapped memory hierarchy with the following specifications.

a. The main memory is 64K bytes

b. The block size is 16 bytes

c. The cache is an I-cache and it has 16 blocks

d. Assume that initially all the blocks are invalid

For each of the following memory accesses determine whether it is a hit (H), compulsory miss (C), or non-compulsory miss (M). Explain your answer in sufficient details.

3. Answer the following questions related to reference addresses:

a. Given a 64-byte cache block, a 4 KB direct-mapped cache (assume byte-addressable), and a 32-bit address reference, which bits would be used for tag, index, and offset.

b. Given a 128-byte cache block a 2 MB 4-way set associative cache (assume byte-addressable), and a 24-bit address reference, which bits would be used for tag, index, and offset.

a. Write to AE b. Read from AC c. Write to B4 d. Read from C7 e. Write to D2 f. Read from F4 g. Write to F7 h. Read from 29 i. Write to 10 j. Read from 2A Set-0 TAG I DO | D1 | D2 | D3 | D4 | D5 | D6 | D7 | V | D | LRU 1010 XXXXXXXX01 1011 X X XX X X X X 1 0 0 Set-1 TAG | DO | DI | D2 | D3 | D4 | D5 | D6 | D7 | V | D LRU a. Write to AE b. Read from AC c. Write to B4 d. Read from C7 e. Write to D2 f. Read from F4 g. Write to F7 h. Read from 29 i. Write to 10 j. Read from 2A Set-0 TAG I DO | D1 | D2 | D3 | D4 | D5 | D6 | D7 | V | D | LRU 1010 XXXXXXXX01 1011 X X XX X X X X 1 0 0 Set-1 TAG | DO | DI | D2 | D3 | D4 | D5 | D6 | D7 | V | D LRU