1. What are Typical Size of Features in Intels 10nm Technology Fin width =? Fin height (active) =? Fin Pitch = ? Gate Length =? Gate pitch = ? Transistor Electrical Width ? Estmate STI Depth Hint: Find IEEE paper intel has published and extracted sizes

2. Draw 2D Process Cuts Perpendicular to Fins P Doped Si N Doped Si NMOS PMOS Add label gate length confirm gate length 27nm? A B B After a) Fin patterning b) oxide filling and planarization c) oxide filling and planarization and recess d) gate/spacer formation e) epitaxial source/drain

Add label gate length confirm gate length 27nm?

3. Draw 2D Cut Perpendicular to Gates Gates lines Sidewall spacer on gate lines STI Fins (surrounded by gates) SubFins STI Top view B B After a) Fin patterning b) oxide filling and planarization c) oxide filling and planarization and recess d) gate/spacer formation e) epitaxial source/drain

4. Show the Few Step Modification To Fabricate Si Nanowire Transistors

5. You are at a Job Interview. Answer the Following question. P Doped Si Draw a schematic of a FinFET and explain how it works

6. Estimate Source/Drain Region Length for TSMC 16nm and 10nm Process Nodes

Find Information on TSMC gate pitch and gate length

Source / Drain Region Length TSMC 16nm/? TSMC 10nm/?

7. Estimates Key Lengths

Gate Length /3 fin Transistor width/ Length (Source/Drain+Gate Use Center to Center S/D

TSMC 16nm /?/?/?

TSMC 10nm /?/?/?

8. Draw a Cross Section Cut Along the Fin for These 2 FinFET Standard Cells P Doped Si A A Hint: read and understand P. Jacob et al. Discussion on fin cut

9. Based on Intels 14nm and 10nm Process technologies . Estimate for Intels 7nm node and short reasoning why P Doped Si Fin width =? Fin height (active) =? Fin Pitch = ? Gate Length =? Gate pitch = ? Transistor Electrical Width ? Estimate STI Depth Hint: Find IEEE paper 14 and 10nm intel has published and extracted sizes