$1)$What is the critical time for LW instructions for full data path shown in appendix. $2)$If only instructions to implement in microprocessor architecture are BEQ, J and SLT$,$ then what will be the clock cycle time. $3)$if only instruction to implement is to 'fetch an instruction' ONLY, then what will be the clock cycle time. $4)$if ALU and REGS latencies can be reduced to $35$ ps each, then what is the critical time for BEQ instruction in the full data path.