1. What type of circuit (combinational or sequential) will be synthesized? Explain why? LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY incomplete_assignment IS port (sel : in std_logic_vector (1 downto 0); A, B : in std_logic; 01, 02: out std logic); END ENTITY; ARCHITECTURE rtl of incomplete_assignment IS BEGIN process (sel, A, B) begin case (sel) is when "00" => 01 01 01 02 01