1. When simulating circuits with Atanua, many of the physical properties of these circuits are discarded. What kind of issues can arise when building and testing a D-Latch master-slave flip flop circuit on a breadboard?

2. What is the difference between the NAND and NOR implementations of an S-R latch?

3. Would duty cycles be of concern when creating Latches or Flip Flops (D-latch, S-R Latch, D-Latch Flip Flop)? Explain.

4.Since one logic gate is used on the 7420, does the other one have any bearing on the operation of the circuit?