(1) With speculation; and assume the outcome of branch instruction is correctly predicted. (2) Assume there is an integer ALU for address calculation; and another integer ALU for branch and all other integer operations. (3) If the first instruction in an issue packet is a branch instruction, only this branch instruction can be issued in this cycle. (4) Up to two instructions can be committed per cycle. (5) There are two CDBs. (6) For load/store, EX is for address calculation. (7) There are ten Reorder Buffer (ROB) entries. (8) Only show the first two iterations and ignore the DADDIU instruction before the loop. Answer Issue Execution R ReadW Memory CDB Write to Commit Comment LD F10, 0(R2) MULD F2, F10, FO LD F8, 0(R3) ADD.D F8, F2, F8 S.D F8, 0(R3) DADDIU R2, R2, #8 DADDIU R3, R3, #8 DSLTU R5, R2, R4 BNEZ, R5, foo LD F10, 0(R2) MULD F2, F10, FO LD F8, 0(R3) ADD.D F8, F2, F8 DADDIU R2, R2. #8 DADDIU R3. R3, #8 DSLTU R5, R2, R4 BNEZ, R5, foo (1) With speculation; and assume the outcome of branch instruction is correctly predicted. (2) Assume there is an integer ALU for address calculation; and another integer ALU for branch and all other integer operations. (3) If the first instruction in an issue packet is a branch instruction, only this branch instruction can be issued in this cycle. (4) Up to two instructions can be committed per cycle. (5) There are two CDBs. (6) For load/store, EX is for address calculation. (7) There are ten Reorder Buffer (ROB) entries. (8) Only show the first two iterations and ignore the DADDIU instruction before the loop. Answer Issue Execution R ReadW Memory CDB Write to Commit Comment LD F10, 0(R2) MULD F2, F10, FO LD F8, 0(R3) ADD.D F8, F2, F8 S.D F8, 0(R3) DADDIU R2, R2, #8 DADDIU R3, R3, #8 DSLTU R5, R2, R4 BNEZ, R5, foo LD F10, 0(R2) MULD F2, F10, FO LD F8, 0(R3) ADD.D F8, F2, F8 DADDIU R2, R2. #8 DADDIU R3. R3, #8 DSLTU R5, R2, R4 BNEZ, R5, foo