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1) Write a single VHDL description with FI(w, x, y, z) = m(0, 2, 5, 7, 10, 12, 13, 14) IIM(1, 3, 5, 7, 10,

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1) Write a single VHDL description with FI(w, x, y, z) = m(0, 2, 5, 7, 10, 12, 13, 14) IIM(1, 3, 5, 7, 10, 12, 13) implemented as a behavioral description and F2(w, x, y, z) implemented as a dataflow description

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