1. You are given the following truth table. A B C D X Y Z 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 0 001 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0 0 001 1 0 1 0 1 0 1 1 1 0 0 1 00 1 1 0 1 0 0 1 1 1 1 1 1 0 1 0 [5X3] Obtain the K-maps and logic functions for X, Y and Z (please note that there might be "do not care" combinations). (m) [5] Draw the logic circuit. 2. 0 [5] Give the truth table of a fulladder and find the functions for sum and carry. (m) [5] Draw the full adder circuit and indicate that there are two half-adders in the circuit. () [5] Give the truth table of a half-subtractor and find the functions for difference and borrow in terms of min-terms. (iv) [s] Use a 2-to-4 line decoder and OR gates to implement the half-subtractor circuit. 3. You are given the following state table. Input Present State Output A B(t) c(t) XY 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 (0) [5] Draw the state diagram. Next State B(t+1) Cit+1) 1 1 1 1 1 1 0 1 1 0 0 0 1 0 1 0 (W) [8] By using K-maps, find the functions for X, Y, B(t+1) and C(t+1). () [7] Draw the sequential circuit (You need to consider D flip-flops as memory unit). 4. 0 [3] What is a shift register? () [10] Draw a 4-bit shift register with parallel load. () (7] Briefly mention the operation of the 4-bit shift register with parallel load. 5. 0 [3] What is the difference between a ripple counter and a synchronous counter? (m) [2] You are asked to design a synchronous counter that will count the sequence 0 > 2>7>0. Represent these decimal numbers in 3 bits binary numbers. () [2] Draw the state diagram of the synchronous counter. (iv) [3] Give the state table of the synchronous counter. () [6] Find the functions for the next state of the state table using K-map. (vi) [4] Draw the synchronous counter (You need to consider D flip-fiops as memory unit)