(10) Write the VHDL model for the combinational part of the following circuit using concurrent statements. Your model should include both an entity and an architecture and you should have a concurrent statement for each gate. You may ignore any annotations. Each gate has a 5 ns delay except for the inverter which has a 2 ns delav, JA J Q KA K Q Clock Box 2 JB J Q KB K Q Box 1 (10) Write the VHDL model for the combinational part of the following circuit using concurrent statements. Your model should include both an entity and an architecture and you should have a concurrent statement for each gate. You may ignore any annotations. Each gate has a 5 ns delay except for the inverter which has a 2 ns delav, JA J Q KA K Q Clock Box 2 JB J Q KB K Q Box 1