10.The figure below shows (left) a map of pipeline instruction registers across several processor cycles and (right) instruction memory from address 0x0000.04FE -50D Assume the PC holds a (cycle 0) current instruction address of Ox0000.0504. Assume all instructions are 16 bits stored little endian. Using the instruction register map below (or a similar one that you draw yourself), fill in the information requested below a) What 16-bit instruction value (in hex) is held in the cycle 0 Fetch register? b) When is this instruction in the Decode register? c) When is it in the Execute register? d) Repeat a)-c) above for the instruction fetched in cycle -1 e) Repeat a)-c) above for the instruction fetched in cycle 1 f) What instruction (in hex) is Executed in cycle 0? address data 0x0.04FE89 C1 0x0.0500 73 37 0x0.0502 1F 1 Instruction Registers -2 -1 1 2 cycles Execute Decode Fetch O0x0.0504 2C1 0x0.0506 3A 22 0x0.0508 49 07 0x0.050A D1 2 0x0.050CE6 2 2-bytes per row view (cycle 0 is current cycle where PC points to fetched instruction) (instructions stored little endian)