11. Estimate the delay of the 8-bit ALU in the figure below assuming 0.1 ns delay for NAND gates, the adder is a CLA(8), and there are only 2-to-1 MUXs available.

Aa-12,80 -1 100 S2 Bit-Wised NOT Bit Wised ORBit-Wised AND Arithmetic Module Wov flag S1 SO Multiplexer (MUX) msk Mask Map n-1 10 ovf f2 fl fo Aa-12,80 -1 100 S2 Bit-Wised NOT Bit Wised ORBit-Wised AND Arithmetic Module Wov flag S1 SO Multiplexer (MUX) msk Mask Map n-1 10 ovf f2 fl fo