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Assume the system has a 256 bit wide bus. The system always reads 64 bytes at a time. How many bus clock cycles does it take from when the CPU first requests the data until 64 bytes have been received? (Note the diagram above may or may not show more or less cycles than necessary.) If the bus operates at 1.25 GHz, how long is a single clock cycle? How many nanoseconds does it take to read 64 bytes from the RAM? The largest data value used in an instruction is an 8 byte double. Why are we concerned with how long it takes to transfer 64 bytes across the bus