(15pts) Answer each of the following with a TRUE (T) or (1) Data in SRAM will be lost without refreshing frequently or FALSE (F) 9. (2) A cache is a small fast memory that stores a subset of the informatio (3) In set associative cache, ory block can be placed in only (4) The unit of data transfer between cache and main memory is a w (5) When CPU requests a word and cannot find it in cache, it a given mem ord. is called a miss. In this case, the requested word will need to be delivered directly from the main memory to the CP (6) Virtual memory is a technique of using main memory as a cache (7) If you can find a value x in the cache, you can find it in the main memory too. (8) Set associative caches decrease the miss rate but are slow when the associativity is increased. (9) for hard drive. Keeping everything else constant, increasing the block size always decreases the miss rate. (10) Write-Back and Write-Through differ in whether data will be ultimately written to the main memory or not Idea pipelined processor has a CPI-1, which is the same as single cycle processor. So they have the same performance. (12) The clock cycle time of a single cycle microprocessor is determined the critical path (w instruction) (13) We need to put the most recently used item in cache according to spatial locality. (14) Structural hazard is caused by data dependence and data hazard is caused by hardware conflict. (15) A major approach for reducing miss penalty is to use split cache