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16. Consider a 32-bit OS that uses two-level paging with PTLRs (Page Table Length Registers). The logical address is divided as follows (from left to

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16. Consider a 32-bit OS that uses two-level paging with PTLRs (Page Table Length Registers). The logical address is divided as follows (from left to right): 9 bits to encode page numbering in the outer page table (1st level), 10 bits to encode the page numbering in the inner page table (2nd level), and 13 bits to encode the offset. The system needs to store a program of size 104,857,600 bytes. PTLRs are registers used by certain computer systems that adopts paging. These registers stores the length of the page table (e.g., outer page table and the last inner page table) in such a way so that a program that does not consume all its logical space will not have page tables with entries that are not used and wasted (viz., Chapter 8, Page 376, in the textbook). 16.1. How many entries do the inner page tables have (2nd level tables)? 16.2. If a single PTE (Page Table Entry), regardless of which level, has a size of 8 bytes, then what is the total size of all page tables together

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