16. In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. TF 17. With asynchronous timing the occurrence of events on the bus is determined by a clock. T F 18. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. TF 19. No single technology is ottimal in satisfying the memory requirements for a computer system. T F 20. A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external. F 21. The processor requires its own local memory. F 22. The unit of transfer must equal a word or an addressable unit. F 23. The L1 cache is slower than the L3 cache. F 24. With write back updates are made in both cache and the main memory. T F 25. It has become possible to have a cache on the same chip as the processor