17. List the three (3) primary steps of the instruction execution cycle, in sequential order a. fetch, decode, memory write b. fetch, memory read, execute c. decode, fetch, execute d. fetch, decode, execute 18. Whi ch flag is set when an unsigned value is too large to fit into a destination operand? a. Sign b. C c. Overflow arry d. Auxiliary Carry 19. Which of the following correctly describes the sequence of reading from memory during a single clock cycle? a. Read line set low; Address placed on bus; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. Address placed on bus; Operand placed on data bus by memory controller; Read line set low; Read line set high, indicating that data bus contains the requested data. b. Address placed on bus; Read line set low; Read line set high, indicating that data bus contains the requested data; Operand placed on data bus by memory controller c. Address placed on bus; Read line set low; Operand placed on data bus by memory controller; Read line set high, indicating that data bus contains the requested data. d. 20. Which register is known as a loop counter? . EAX b. EBX c. ECX d. EDX 21. Which mode is the native state of the Intel processor? a. Protected mode b. Virtual-8086 mode c. Real-address mode d. System management mode 22. Which type of RAM is typically used for cache memory? a. Static RAM b. Dynamic RAM c. CMOS RAM d. Video RAM Page 3 of 8