. (19 pts) write the VHDL code Entity (Midterm2) / Architecture (Mixed) pair for the following circuit diagram, which uses two component instantiations of the circuit described in problem 5. Use a mixed structural and dataflow style only (no behavioral VHDL and processes). -R+ Midterm / Schem FY -C+ M(O) M(1)++ M(2) AH -B> Midterm / Schem -SH FZ-H . (19 pts) write the VHDL code Entity (Midterm2) / Architecture (Mixed) pair for the following circuit diagram, which uses two component instantiations of the circuit described in problem 5. Use a mixed structural and dataflow style only (no behavioral VHDL and processes). -R+ Midterm / Schem FY -C+ M(O) M(1)++ M(2) AH -B> Midterm / Schem -SH FZ-H