1a) (5pts) Provide a diagram of a half-adder

1b) (5pts) Provide a diagram of a full-adder constructed from two half-adders

2a) (5pts) Provide a diagram for a single-bit memory constructed from a multiplexor.

2b) (5pts) Provide a diagram for a single-bit JK memory edge-triggered flip-flop

2c) (10pts) Provide a diagram for a multiplexor/demultiplexor pair, with four inputs and outputs, and control lines as needed. Use two-input gates in positive logic.

please can you help me with this question?