2. [15 points] Suppose that a buggy implementation of the MIPS pipeline does not forward the write register # through the ID/EX, EXMEM, and MEM/WB interstage buffers. Instead, it directly feed the output of the MUX controlled by RegDst as shown: Write register Write data RegDst Instr[20-16 0 M Instr[15-11 X IF/ ID/EX EX/MEM MEM/WB Everything else in the pipeline is implemented as shown on the above diagram. For sw instruction, the control signal RegDst is actually X (don't care), but let's assume that it is set to 0 for sw Suppose that, initially, $t1=0x1000, $t2=0x2000, $t3=0x3000, and $t4=0x4000. Consider the execution of the following code in this buggy pipeline. Determine the final values of the $t1, $t2, and $t3 registers after all the instruction leave the pipeline add $tl, $t2, $t3 sw $t2, 0x0000 ($t4) Sw $t2, 0x1000 ($t4) add $t2, $t3, $t4 s $t3, 0x2000 ($t4) Sw $t3, 0x3000 ($t4) Sw $t3, 0x4000 ($t4) #1 #2 #3 #4 #5 #6 #7 2. [15 points] Suppose that a buggy implementation of the MIPS pipeline does not forward the write register # through the ID/EX, EXMEM, and MEM/WB interstage buffers. Instead, it directly feed the output of the MUX controlled by RegDst as shown: Write register Write data RegDst Instr[20-16 0 M Instr[15-11 X IF/ ID/EX EX/MEM MEM/WB Everything else in the pipeline is implemented as shown on the above diagram. For sw instruction, the control signal RegDst is actually X (don't care), but let's assume that it is set to 0 for sw Suppose that, initially, $t1=0x1000, $t2=0x2000, $t3=0x3000, and $t4=0x4000. Consider the execution of the following code in this buggy pipeline. Determine the final values of the $t1, $t2, and $t3 registers after all the instruction leave the pipeline add $tl, $t2, $t3 sw $t2, 0x0000 ($t4) Sw $t2, 0x1000 ($t4) add $t2, $t3, $t4 s $t3, 0x2000 ($t4) Sw $t3, 0x3000 ($t4) Sw $t3, 0x4000 ($t4) #1 #2 #3 #4 #5 #6 #7