You are designing a PMD and optimizing it for low energy. The core, including an $8KBL1$ data cache, consumes $1W$ whenever it is not in hibernation. If the core has a perfect $L1$ cache hit rate, it achieves an average CPI of $1$ for a given task, that is$,1000$ cycles to execute $1000$ instructions. Each additional cycle accessing the L$2$ and beyond adds a stall cycle for the core. Based on the following specifications, what is the size of L$2$ cache that achieves the lowest energy for the PMD $($core$,$ L$1,$ L$2,$ memory$)$ for that given task?

a$.$ The core frequency is $1GHz,$ and the L$1$ has an MPKI of $100.$

b$.$ A $256KB$ L$2$ has a latency of $10$ cycles, an MPKI of $20,$ a background power of $0\mathrm{.}2W,$ and each $L2$ access consumes $0\mathrm{.}5nJ.$

c$.$ A $1$ MB L$2$ has a latency of $20$ cycles, an MPKI of $10,$ a background power of $0\mathrm{.}8W,$ and each $L2$ access consumes $0\mathrm{.}7nJ.$

d$.$ The memory system has an average latency of $100$ cycles, a background power of $0\mathrm{.}5W,$ and each memory access consumes $35nJ.$