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2. A simple digital lock works as follows. The lock has two positions: locked and unlocked. There are three buttons to operate the lock: 0,1,

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2. A simple digital lock works as follows. The lock has two positions: locked and unlocked. There are three buttons to operate the lock: 0,1, and . Pressing the sequence 0, 1,0 will open the lock, while pressing at any time will close it. Time is measured in units (clock cycles), and not pressing any button means pressing an imaginary B (blank) button in the given clock cycle. Blanks are added automatically to the input sequence, if necessary (i.e., while the operator is thinking). The blank will not destroy any correct prefix that has already been entered. To retry after of 0,1,0 (with possible blanks interjected) as a suffix in an arbitrary input sequence will open the lock, which will remain open until is entered. As a finite automaton (DFA) with output, the lock has four input symbols. Encode these input symbols as: 01 for 0, 10 for 1, 11 for*and 00 for B. Regarding the two positions: 0 for locked and 1 for unlocked. In each transition step, the output should be identical to the new! position, and the initial position is 0. The positions are not! the states of the automaton being described. It is your task to figure out how many states are necessary, and what is their relationship with the position of the lock. a) Specify the transition diagram of the finite automaton M described above. Is M Mealy or Moore type? Is M asynchronous? b) Design a state machine for M based on the given encoding. Use master-slave latch pairs in your state register, and rely on the one-hot design technique to keep r combinational logic simple c) Redesign the state machine in b) using edge-triggered D flip-flops in your state register. The output in that design should be identical to the position of the lock in the current! state at all times d) Add a reset input to be able to adjust the initial state of the state register. Can you make the reset work through the already existing input *? A synchronous reset is sufficient

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