2. A single cycle processor has a period of 10 ns. The same processor can be designed with a multicycle pipeline implementation with a period of 7.5 ns. Assuming no hazards /stalls, what is the minimum number of instructions needed before any speedup is realized? How many instructions (with no stalls or hazards) would you need to execute before the multicycle implementation gives you 3x speedup relative to a single cycle processor? What is the maximum speedup this pipeline can achieve? a. b. c