2. An ideal pipeline will run a sequence of instructions with no delay. As usual, suppose that each stage takes one clock cycle. That is, given instructions I1, , Ik running in this ordering, in the first clock cycle, I1 is in the first stage of the pipeline, in the second clock cycle, I1 is in the second stage of the pipeline and I2 is in the first stage of the pipeline, etc. Let Nk be the number of cycles needed till the last instruction Ik moving out of the pipeline. Prove that lim k Nk k = 1.