2. Assume that individual stages of the datapath have the following latencies: Fetch Decode Execute Memory WriteBack 150 ps 250 ps 350 ps 300 ps 200 ps What is the clock cycle time in a pipelined and non-pipelined processor? What is the total latency of an LW instruction in a pipelined and non-pipelined processor? If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (15 points)