2. Assume the reference inverter (Gate 1 to the left of the logic chain) has nMOS and pMOS transistors of width 1 fin each. Assume the load Cout at the output of the chain (driven by Gate 3 to the right of the logic chain) has a capacitance equal to 4096X of CIN, the input capacitance of Gate 1. (i) Calculate the fan-out factor along the chain to minimize total propagation delay (ii) Size the transistor widths of each gate given this fan-out factor