$2$ caches are $1$ and $6$ clock cycles respectively. The miss penalty of L$2$ cache is $20$ clock cycles. The miss rate of L$1$ cache is twice that of L$2.$ The average memory access time of the cache system is $4$ cycles. Calculate the miss rates of L$1$ and L$2$ caches.

Let $Z$ represents the $\%$Miss rate of $L2$