2. Consider the following code: addi $s0, $s0, 4 addi $s0, $s0, 4 add $to, Sto, $t1 lw St2, 0 (Sso) addi $s0, $s0, 4 add $t0, $t0, $t2 Assuming the processor has full forwarding, populate the following pipeline diagram using the compact notation (Use S for stalls) a. Assuming the processor has full forwarding and the processor can issue one load/store instruction and one ALU type instruction at a time (Static Dual Issue), populate the following pipeline diagram using compact notation (Use S for stalls). Assume a stall in on instruction will also cause a stall in the dual instruction. b. 2. Consider the following code: addi $s0, $s0, 4 addi $s0, $s0, 4 add $to, Sto, $t1 lw St2, 0 (Sso) addi $s0, $s0, 4 add $t0, $t0, $t2 Assuming the processor has full forwarding, populate the following pipeline diagram using the compact notation (Use S for stalls) a. Assuming the processor has full forwarding and the processor can issue one load/store instruction and one ALU type instruction at a time (Static Dual Issue), populate the following pipeline diagram using compact notation (Use S for stalls). Assume a stall in on instruction will also cause a stall in the dual instruction. b