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2. Consider the following sequence of instructions add $to, $s0, $s1 sub $t0, Sto, $s2 lw $t1, 60ISto) and $t2, St1, $to sw $t2, 5St5)
2. Consider the following sequence of instructions add $to, $s0, $s1 sub $t0, Sto, $s2 lw $t1, 60ISto) and $t2, St1, $to sw $t2, 5St5) or $t5, $s2, $s3 a. Indicate dependences and their type (RAW, WAW, WAR) b. If there is no forwarding or hazard detection, insert nop to ensure correct execution. . If forwarding and hazard detection are implemented, show the pipeline execution diagram for the entire code. This the pipeline diagram for the first instruction Clock cycle add Sto, $s0, 1 IF ID EX MEM WB sub St0, Sto, $s2 w $t1, 60(Sto) and $12, $t1, $to sW $t2, 5( $t5) or $t5, $s2, $s3 d. Are there any pipeline stalls due to data hazards in part c? rearranging the code? If yes, explain how by showing rearranged code below. Can the stall(s) be prevented by e. Assume the following cycle times: Without forwarding With full forwarding 250 ps What is the total execution time of this instruction sequence without forwarding, and with full forwarding. What is the speed up achieved in this case, by adding full forwarding and hazard detection? 300 ps
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