2. Consider the matrix_add function shown below: 1232710 107 4 5 6 } int matrix_add(int a[128] [128], int b[128] [128], int c[128] [128]) { int i, j; for(i = 0; i < 128; i++) for(j=0;j < 128; j++) return 0; c[i][j] = a[i][j] + b[i][j]; In each iteration, the compiled code will load a[i][j] first, and then load b[i][j]. After performing the sum of those two values, the result will be stored in c[i][j]. The processor has a 64 KiB, 2-way, 64 byte-block L1 data cache, and the cache uses an LRU policy for determining which cache line to evict if a set is full. The L1 data cache is write-back and write-allocate. For the following questions, assume that the addresses of the a, b, and c arrays are 0x10000, 0x20000, and 0x30000, respectively, and that the cache starts out completely empty. Explain all of your answers. (a) (12.5 points) What is the L1 data cache miss rate for the matrix_add function? How many misses are contributed by compulsory miss? How many misses are conflict misses? (b) (12.5 points) If the L1 hit time is 1 cycle, and the L1 miss penalty is 20 cycles. What is the average memory access time?