2. Considering a direct-mapped Cache for a MIPS processor, (a) If the cache contains 256 8-word blocks, how many number of bits for the tag field? (496) (b) What is the size of the cache memory? Please also specify the number of entries and word-length of each entry, respectively. Do remember to include the "valid" bit. (For example: 8 entries x 12 bits/entry-96 bits.) (696) cache. (5%) the slide. (10%) (c) Find the block index of the MISP instruction with address 2018 if it is in the (d) Please draw the block diagram of the cache such as the figure on page 32 of