2. Design a 3-bit carry-look-ahead adder (1-level of CLA). Make sure to show the design of the basic block used in the adder (i.e. FA with carry logic removed) as well as the logic that generates all carries. Give the delay of each output signal in the unit assuming that the delay of any gate is ranputs/47 regardless of gate type where? 7 is the ceiling function. For example, a five input AND gate has a delay of?s/ =?1.2$1-2. 3. Design an 32-to-1 multiplexer using only 8-1 and/or 4-1 multiplexors. Give the short hand truth table for this multiplexor(i.e. similar to table in figure 6.7b in your textbook) 4. Design a 4-to-16 decoder using only smaller decoders. Make sure to clearly label your inputs, outputs and control signals. Assume inputs are labeled as As.oand output are labeled as O1s.o