2. Experimentally verify the JK flip-flop state table with the following circuit. Is the JK flip-flop positive or negative edge triggered? Verify the Characteristic table. JK Flip Flop Test 1 00 CLKO 0 Kt eno Q' Kl 0 When 1, pin state to 1 0 When 0, clock ineffective When 1. pin state to 0 0 Reference: The characteristic equation of the JK flip-flop is Q(t+1) = JQ'(t) + K'Q(t). Characteristic Table Excitation Table 3 K Q(t+1) Operation Q(t) Q(t+1) JK 0 0 0(t) No Change 0 0 0 1 Reset 0 1 1 x 1 0 1 Set 1 0 1 1 i '(t) Complement 1 1 0 3. Design a 3 bit counter which follows the sequence 0 -> 2-> 3 -> 4 ->7->0. Note: The following are required for the lab Assignment: o Follow the sequential design procedure which is presented in the lab lecture notes. o To make marking easier, route all the unused states to state 7. . Use JK flip-flops in your counter circuits. Hand in: Show your design steps and the resulting circuit in Logisim. Describe your testing procedures