2. For a given processor, assume there are no stalls. The breakdown of executed instructions are as given in Table below: add 20% a. addi not beq Iw SW 20% 0% 25% 25% 10% In what fraction of all cycles is the data memory used? Why? In what fraction of all cycles is the input of the sign-extend circuit needed? Why? What is this circuit doing in cycles in which its input is not needed? b