2 For this problem, refer to the the figure below that shows the initial state of caches and directories for 4 CPU distributed memory machine. Each node is allocated with a memory range shown at the bottom of the figure where the directories and memories are drawn as unified for simplicity. 08 Coherence State Address Data Coherence State Coherence Address Cara Data M 20 5 0 10 BO M OF 5 5 5 OF 01 5 Coherence State Address Data 08 5 14 00 01 5 Address State Share Address State Sharer Data Address State Data Address State Sharer Dat M (POP) + UC 1 01 UC " 23 12 UC " 41 5 (POP) 5 OF 9 UC " 2 UC " UC " 78 2 UC " 7 UC 0 11 UC 0 17 12 UC " 23 OF 24 5 00 15 UC " PO Maddresses: 0-3 P1 Maddresses: 4-7 Each question specifies a CPU operation of the form: P#: P2 Maddresses: 8-11 [