2. Modify the below VHDL code (four-bit up-counter) by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; cee, ENTITY upcount IS PORT (Clock, Resetn, E : IN STD LOGIC ; : OUT STDLOGIC VECTOR (3 DOWNTO 0)); END upcount; ARCHITECTURE Behavior Of upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN PROCESS ( Clock, Resetn) BEGIN IF Resetn = '0' THEN Count